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Freescale Semiconductor /MK11D5WS /SIM /CLKDIV2

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Interpret as CLKDIV2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED

Description

System Clock Divider Register 2

Fields

RESERVED

no description available
RESERVED

no description available
RESERVED

no description available

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data